harrydfoster's blog

SystemC 2011 Standard Published

Posted Fri, 2012-01-20 04:15

IEEE Std. 1666™-2011 Available as Free Download In November 2011 I blogged the IEEE Standards Association (SA) approved a revision to the popular SystemC standard, known officially as IEEE Std. 1666™-2011.  One of the key elements of this standard includes the addition of Transaction Level Modeling (TLM).  I pointed to several online resources to learn [...]

Verification solutions that help reduce bug cost

Posted Sun, 2012-01-08 11:30

I think very few engineers would argue with the claim that the longer a bug goes undetected, the more expensive it is to fix. In fact, the general rule-of-thumb is that the cost to fix a bug increases by an order of magnitude as a project progresses from one milestone to the next. Bugs found [...]

Instant Replay for Debugging SoC Level Simulations

Posted Tue, 2011-12-13 18:15

Instant Replay Offers Multiple Views at Any Speed If you’ve watched any professional sporting event on television lately, you’ve seen the pressure put on referees and umpires.  They have to make split-second decisions in real-time, having viewed ultra-high-speed action just a single time.  But watching at home on television, we get the luxury of viewing [...]

2011 IEEE Design Automation Standards Awards

Posted Tue, 2011-12-06 04:15

The DASC Participates in IEEE Standards Association Gala Event The IEEE Computer Society Design Automation Standards Committee (DASC) participated in the annual IEEE Standards Association (SA) Award ceremony held in New Brunswick, NJ USA  on 4 December 2011.  Hundreds met to recognize the work of thousands who volunteer daily to develop standards and to honor [...]

Overridden with Overrides

Posted Tue, 2011-11-22 13:30

The word override is heavily overloaded in object oriented programming. This concept can make object-oriented programming very difficult to understand. Ironically, the very concept of object-oriented programming came from a simulation language called “Simula” in the 1960′s. Both Verilog and C++ are descendants of this language, but took different paths along the way to represent [...]

Getting started with the UVM – Using the Register Modeling package

Posted Mon, 2011-11-14 18:30

Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is no getting over the fact that if you are going to develop any reasonably sized testbench in SystemVerilog, you need to learn how to declare and construct a class. You also need to learn a [...]

Getting started with the UVM – Using the Register Modeling package

Posted Mon, 2011-11-14 17:00

Adopting SystemVerilog can be challenging to some, and learning the UVM at the same time might seem overwhelming. There is no getting over the fact that if you are going to develop any reasonably sized testbench in SystemVerilog, you need to learn how to declare and construct a class. You also need to learn a [...]

TLM Becomes an IEEE Standard

Posted Thu, 2011-11-10 14:45

IEEE Announces Revision to IEEE 1666™ – Adds Transaction-Level Modeling Support A significant step forward to address standards for advanced system-on-chip (SoC) designs has taken place by the IEEE.  The IEEE announced the new revision of the SystemC standard, known as IEEE 1666™-2011, has been approved.  While it is a revision of the current SystemC [...]

Posted Wed, 2011-11-09 16:45

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Posted Fri, 2011-11-04 16:45

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